Honored Contributor3 Questions:Does terminal resistance needed in driving high speed ADC through difference clock output pin?
How much is the jitter of CYCLONE3 pll output? How far should LVDS output pins away from Clock output pins? Thanks
Honored Contributor1. Depends on the I/O standard, for LVDS: by design, for others possibly
2. PLL jitter is specified in the datasheet. If you intended low jitter, e.g. for a communication receiver, you better drive the ADC from an external clock source directly 3. Output pins? Quartus won't require a distance for a differential clock output, I think.Honored ContributorThank you for your reply.
1.I mean that difference clock output is a type of lvds signal, will it be used exactly like lvds? 3.I think LVDS signal should not be too close to digital signals,especial to high frequency signals.is that right?Honored ContributorYou should, know if the ADC expects LVDS or high level diffential clock.
