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Altera_Forum
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16 years ago

Clock diff output need terminal resistance ?

3 Questions:Does terminal resistance needed in driving high speed ADC through difference clock output pin? How much is the jitter of CYCLONE3 pll output? How far should LVDS output pins away fro...
Altera_Forum's avatar
Altera_Forum
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16 years ago

1. Depends on the I/O standard, for LVDS: by design, for others possibly

2. PLL jitter is specified in the datasheet. If you intended low jitter, e.g. for a communication receiver, you better drive the ADC from an external clock source directly

3. Output pins? Quartus won't require a distance for a differential clock output, I think.