Altera_ForumHonored Contributor15 years agoClock diff output need terminal resistance ? 3 Questions:Does terminal resistance needed in driving high speed ADC through difference clock output pin? How much is the jitter of CYCLONE3 pll output? How far should LVDS output pins away fro...Show More
Altera_ForumHonored Contributor15 years agoYou should, know if the ADC expects LVDS or high level diffential clock.
Recent DiscussionsDK-DEV-AGI027-RA QSPI Verification FailsCyclone 5 SoC FPGA Bank Supply PrerequisiteAGILEX 5 Migration issueTo INTEL - Request for Compliance Data from Analog Devices, IncArria 10 GX RX max intra-differential pair skew