vernaNew Contributor3 years agoclock control signal problem on Cyclone V GT I'm working with the Cyclone V GT development board.My design only needs to use frequency divider to get the signal, I tried to use 240MHz to divide the frequency and can get the signal successfully,...Show More
SyafieqSSuper Contributor3 years agoHi Chuang,I found some discussion might be useful related to clock divider.Please take a lookhttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Best-way-to-code-a-clock-divider/td-p/123104
Recent DiscussionsLooking for the Document ID 854068SolvedAbout floating voltage of the Agilex 3 power on resetSuggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAImplementation of lower data rate.