Clock Control and Clock Mux

Hi

Basically, i have 2 designs which are almost the same. In the design, the pll output(3 output) route it to the clock mux. Then, the output of clk mux is routed to main core and output port. The only different is the clock mux. One is using altera megafunction clkmux and another is mux i design by myself.

The design is attached. However, the post fitting of pll is different for design 1 and design 2. My intention is to eliminate the CLKCTRL in PLL block. Is there any way to do it?

The reason is the CLKCTRL(extra clock delay) make my timing failure.

Thanks