Classic Timing Analyzer

In the timing analyzer report, it was mentioned that Fmax is restricted to 237.53 MHz, but by viewing the critical path :

The summation of the delays is not 4.21 so why the frequency is restricted to this value?

Here are the delays :

Info: Clock "CLK" Internal fmax is restricted to 237.53 MHz between source register "countfsm:u2|PS.seventeen" and destination register "countfsm:u2|Q_reg1[2]"

Info: fmax restricted to clock pin edge rate 4.21 ns. Expand message to see actual delay path.

Info: + Longest register to register delay is 1.184 ns

Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X113_Y31_N9; Fanout = 4; REG Node = 'countfsm:u2|PS.seventeen'

Info: 2: + IC(0.405 ns) + CELL(0.284 ns) = 0.689 ns; Loc. = LCCOMB_X113_Y31_N0; Fanout = 2; COMB Node = 'countfsm:u2|WideOr3~10'

Info: 3: + IC(0.236 ns) + CELL(0.154 ns) = 1.079 ns; Loc. = LCCOMB_X113_Y31_N16; Fanout = 1; COMB Node = 'countfsm:u2|WideOr2'

Info: 4: + IC(0.000 ns) + CELL(0.105 ns) = 1.184 ns; Loc. = FF_X113_Y31_N17; Fanout = 1; REG Node = 'countfsm:u2|Q_reg1[2]'

Info: Total cell delay = 0.543 ns ( 45.86 % )

Info: Total interconnect delay = 0.641 ns ( 54.14 % )

Info: - Smallest clock skew is 0.000 ns

Info: + Shortest clock path from clock "CLK" to destination register is 3.219 ns

Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'CLK'

Info: 2: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = IOIBUF_X0_Y36_N1; Fanout = 1; COMB Node = 'CLK~input'

Info: 3: + IC(0.188 ns) + CELL(0.000 ns) = 1.020 ns; Loc. = CLKCTRL_G4; Fanout = 23; COMB Node = 'CLK~inputclkctrl'

Info: 4: + IC(1.591 ns) + CELL(0.608 ns) = 3.219 ns; Loc. = FF_X113_Y31_N17; Fanout = 1; REG Node = 'countfsm:u2|Q_reg1[2]'

Info: Total cell delay = 1.440 ns ( 44.73 % )

Info: Total interconnect delay = 1.779 ns ( 55.27 % )

Info: - Longest clock path from clock "CLK" to source register is 3.219 ns

Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'CLK'

Info: 2: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = IOIBUF_X0_Y36_N1; Fanout = 1; COMB Node = 'CLK~input'

Info: 3: + IC(0.188 ns) + CELL(0.000 ns) = 1.020 ns; Loc. = CLKCTRL_G4; Fanout = 23; COMB Node = 'CLK~inputclkctrl'

Info: 4: + IC(1.591 ns) + CELL(0.608 ns) = 3.219 ns; Loc. = FF_X113_Y31_N9; Fanout = 4; REG Node = 'countfsm:u2|PS.seventeen'

Info: Total cell delay = 1.440 ns ( 44.73 % )

Info: Total interconnect delay = 1.779 ns ( 55.27 % )

Info: + Micro clock to output delay of source is 0.230 ns

Info: + Micro setup delay of destination is -0.018 ns

Thanks in advance.