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Altera_Forum
Honored Contributor
13 years agoQuartus infers RAM when possible; that is, it uses the dedicated RAM blocks to store information, instead of using registers.
The RAM blocks cannot be used as flexibly as registers, though. Therefore, RAM blocks can only be inferred when the code describes behavior that can actually be implemented using block RAMs. Below, the code for a basic dual-port, same clock, 16x1024 memory which will be inferred into RAM blocks. Although Quartus is smart enough to infer RAM blocks from more complicated code, when in doubt it's best to have a clear piece of code for the RAM and work from there.reg myMemory ;
// Port A
wire addressA;
wire dataInA;
wire writeEnableA;
reg dataOutA;
// Port B
wire addressB;
wire dataInB;
wire writeEnableB;
reg dataOutB;
always @ (posedge clk) begin
if (writeEnableA) begin
myMemory <= dataInA;
dataOutA <= dataInA;
end
else
dataOutA <= myMemory;
if (writeEnableB) begin
myMemory <= dataInB;
dataOutB <= dataInB;
end
else
dataOutB <= myMemory;
end
// Write logic needs to control address*, writeEnable* and dataIn*
// Read logic needs to control address* and gets data from dataOut*