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Altera_Forum's avatar
Altera_Forum
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16 years ago

Check for broken CPLD

Hi,

What is the best way to determine if a CPLD is damaged?

I am having trouble with my design and so far there are two symptoms:

1. Most of the time when I try and program I get an error: cannot access jtag chain.

This is solved by going into the JTAG Chain debugger and continually pressing Test JTAG Chain until my device is successfully detected, at which point it can then be programmed.

The Test JTAG Chain commands usually returns an assortment of "unknown integrity checking failures" and a number of detections of 2-3 unknown devices before it will detect my MAXII.

2. One part of my design isn't working correctly. I would usually attribute this to an error in my VHDL but I don't think it can be. The functionality is very simple (its an implementation of an SPI slave) and sometimes it works and sometimes it doesnt. I could understand there being bugs in softwrae but VHDL is not software, it doesnt have a runtime and therefore it should either always work or always break - as it is it looks like a register is being corrupted, I didnt know that could happen inside a CPLD.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    If you are taking several attempts for the chain integrity test to pass, it suggests some signal level/termination issues on your design.

    A symptom of this could be that during programming the data is being corrupted and hence the program (SPI slave) not working as you expect.

    Try an oscilloscope probe on the TCK pin during testing/programming. The probe capacitance can sometimes help in altering the signal termination.

    Also the JTAGLIve (www.jtaglive.com (http://www.jtaglive.com)) free utility Buzz includes an alternative

    integrity/infrastructure test that works with the USB-Blaster and returns more information.

    BR

    Paul
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi Paul_Mac, thanks for your reply.

    I have managed to sort out the JTAG errors, it was down to improper termination on the board and it is much more stable now.

    The problem I had with the functionality is 'sort of' solved. The communication is working now, although I have a great deal of error checking in which I read back the entire transmission to the uC to ensure that it is transferred correctly since I was getting so many errors.

    However, this wasn't the fix, what I did was drop the, supposedly independant, system clock from 66Mhz to 33MHz. What is strange is that Quartus indicated I could drive the system clock to 120Mhz at least. ~40Mhz is acceptable for my application, though certainly being limited to that isn't ideal. I am guessing it is some quirk of the synthesized circuit and I don't suppose ill ever know exactly whats going on.

    Thanks alot for that link to Buzz, that looks Very handy; I don't have a USB Blaster yet but that program might be enough to get me to get one finally.