Check for broken CPLD

Hi Paul_Mac, thanks for your reply.

I have managed to sort out the JTAG errors, it was down to improper termination on the board and it is much more stable now.

The problem I had with the functionality is 'sort of' solved. The communication is working now, although I have a great deal of error checking in which I read back the entire transmission to the uC to ensure that it is transferred correctly since I was getting so many errors.

However, this wasn't the fix, what I did was drop the, supposedly independant, system clock from 66Mhz to 33MHz. What is strange is that Quartus indicated I could drive the system clock to 120Mhz at least. ~40Mhz is acceptable for my application, though certainly being limited to that isn't ideal. I am guessing it is some quirk of the synthesized circuit and I don't suppose ill ever know exactly whats going on.

Thanks alot for that link to Buzz, that looks Very handy; I don't have a USB Blaster yet but that program might be enough to get me to get one finally.