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Altera_Forum's avatar
Altera_Forum
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16 years ago

Changing frequency of the system

Hi I was interested in knowing if there is any way in which I could change the frequencies that various components on my FPGA ran at, without actually going through the entire synthesis process.

The point is that we would like to emulate the system for a large number of different frequencies and as a result the relatively very high overhead of going through synthesis everytime is unacceptable.

Is is it possible to somehow hack the PLL module frequencies in the .sof file or maybe generate a bunch of clocks and reroute them post synthesis. Will the quartus smart_compile option help me out here ?

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    Hi I was interested in knowing if there is any way in which I could change the frequencies that various components on my FPGA ran at, without actually going through the entire synthesis process.

    The point is that we would like to emulate the system for a large number of different frequencies and as a result the relatively very high overhead of going through synthesis everytime is unacceptable.

    Is is it possible to somehow hack the PLL module frequencies in the .sof file or maybe generate a bunch of clocks and reroute them post synthesis. Will the quartus smart_compile option help me out here ?

    Thanks

    --- Quote End ---

    Hi,

    what is the frequency range you would like to test ? How many clocks do you use in your design ?

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    There are various options to achieve what you intend. The most comfortable solution is to add an ALTPLL_RECONFIG Megafunction (if supported by the respective FPGA family) and control the parameter e.g. by a Source and Probe instance. A more basic method is to edit the PLL parameters by the Chip Editor and perform the fairly fast Engineering Change flow, that involves only part of the fitter. I used the method to evaluate the clock phase for LVDS SERDES.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks a lot for the Reconfigurable pll suggestion, will check it out. Seems ideal for my requirements :)

    @Pletz

    The clock frequencies would vary by about +-20% of nominal values for instance , and the design would have around 3 to 4 tunable clocks. I am trying to emulate a multiple frequency based design which communicates via FIFO's and want to measure system performance as a function of different frequencies.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    Thanks a lot for the Reconfigurable pll suggestion, will check it out. Seems ideal for my requirements :)

    @Pletz

    The clock frequencies would vary by about +-20% of nominal values for instance , and the design would have around 3 to 4 tunable clocks. I am trying to emulate a multiple frequency based design which communicates via FIFO's and want to measure system performance as a function of different frequencies.

    --- Quote End ---

    Hi,

    you should follow FvM suggestions.

    Kind regards

    GPK