Changing frequency of the system

There are various options to achieve what you intend. The most comfortable solution is to add an ALTPLL_RECONFIG Megafunction (if supported by the respective FPGA family) and control the parameter e.g. by a Source and Probe instance. A more basic method is to edit the PLL parameters by the Chip Editor and perform the fairly fast Engineering Change flow, that involves only part of the fitter. I used the method to evaluate the clock phase for LVDS SERDES.