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Hi I was interested in knowing if there is any way in which I could change the frequencies that various components on my FPGA ran at, without actually going through the entire synthesis process.
The point is that we would like to emulate the system for a large number of different frequencies and as a result the relatively very high overhead of going through synthesis everytime is unacceptable.
Is is it possible to somehow hack the PLL module frequencies in the .sof file or maybe generate a bunch of clocks and reroute them post synthesis. Will the quartus smart_compile option help me out here ?
Thanks
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Hi,
what is the frequency range you would like to test ? How many clocks do you use in your design ?
Kind regards
GPK
Honored Contributor
