Center aligned output clock for ALTLVDS_TX in external PLL mode (Arria V)

I am using the ALTLVDS_TX core for transmitting differential data that was previously received by the ALTLVDS_RX core. The target device is an Arria V FPGA. The input/output data rate is 800 Mbps (400 MHz DDR clock).

To avoid having an asynchronous clock domain crossing between RX and TX I am using the ALTLVDS cores in external PLL mode as described in UG-MF9504. The data received by the ALTLVDS_RX core is center-aligned (as opposed to edge-aligned which is the case discussed in UG-MF9504).

As suggested by the user guide, I first generated the ALTLVDS_RX and ALTLVDS_TX cores using the internal PLL mode to determine the PLL parameters (frequency, phase shift, duty cycle) for the required PLL clocks. I then switched to external PLL mode and instantiated a PLL with the corresponding parameters.

The problem is that in external PLL mode there is no way to specify a phase shift for the ALTLVDS_TX output clock (tx_outclock) which is required to that the output data is center aligned with the output clock.

I added an additional output clock to the PLL with the desired frequency (400 MHz) and phase shift with respect to the ALTLVDS_TX output data. The resulting wave-form is correct according to the simulation. However, when measuring on the board the TX clock and data are not center aligned.

Is there a way to achieve center-aligned output clock when using the ALTLVDS_TX core in external PLL mode?