Center aligned output clock for ALTLVDS_TX in external PLL mode (Arria V)

Hi

when generating a ALTLVDS_TX using the MegaWizard, it is not possible to specify a phase shift is the "Use external PLL" option is selected.

For the PLL I am using the phase shifts reported in the resource report when using internal PLL for my setup (as suggested in this document https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altlvds.pdf (see page 51)).

Is there any example PLL configuration for ALTLVDS_TX with center-aligned clock/data?