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SWrig4's avatar
SWrig4
Icon for New Contributor rankNew Contributor
8 years ago

Center aligned output clock for ALTLVDS_TX in external PLL mode (Arria V)

I am using the ALTLVDS_TX core for transmitting differential data that was previously received by the ALTLVDS_RX core. The target device is an Arria V FPGA. The input/output data rate is 800 Mbps (40...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
8 years ago

Hi,

To achieve center-aligned adjust the phase shift of external pll.

Can you recheck the phase shift setting of external pll.

Do refer below links for more information.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06142011_962.html

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/functionality/pll-clocking-stratix3.html

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)