case analysis and false path issues

Open the word document at and look at page 18, Dedicated DDR Output:

http://www.alteraforum.com/forum/showthread.php?t=4806&highlight=source+synchronous

You can see how the clock path is the ONLY relevant path through the DDR cell. That document was written a long time ago, and I think TimeQuest now automatically puts a false path on the registers(behind the scenes) so you only see the clock path through it. That is good, as the registers change doesn't cause the output to change, and instead it's the select path that you want.

This is a thing called "Clock as Data", whereby the source clock doesn't feed the clock of the source register, and instead directly feeds the D input(or any input besides the clock) fo the destination register. It still might not meet timing, but the path sounds correct.