case analysis and false path issues

Thank you for the response.

I agree with you that the false path should work and the cell is a DDIOOUTCELL.

The tool (TimeQuest) does recognize the the pins and command "set_false_path -through [get_pins {path to muxsel}] " in the sdc constraint file but the element muxsel still shows up in timing report of Data Required Path. What am I missing here?

Also, I added the constraint in the sdc file that the launch clock and latch clock which are of two different domains are a specific max. delay apart. The negative slack still shows up.

Please correct me if I am wrong anywhere.