case analysis and false path issues

There is no Case Analysis, but from my understanding, that's not what you want. Basically the select line of the mux is not what you want analyzed, so you want a False Path on it. Be sure to apply it using the get_pins option(use the Name Finder) and the -through. That should work.

That being said, when the clock drives the select of the mux, you've basically got a double-data rate output going. I don't know if this architecture is in the I/O or the fabric, but in general I would argue that the clock change is relevant, since it's what causes the data value to change. In fact, the devices that have DDR registers in their I/O cells, the delays are creates such that the ONLY thing that matters is the clock through the mux select. This makes the output glitch-free.