Cascading CPLDs on different PCBs

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I quite like the RS485 solution but I wonder if it's overkill. All the daughtercards will be located quite close. Still, I'd rather play it safe.

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Its easy to put an RS485/422 driver/receiver footprint on a board, and assign differential pins to the header, but then also have a resistor that jumps the single-ended CPLD output onto the positive signal of the differential, you can also have a pull-down to gnd on the negative side of the differential too. That way you can load the board as LVCMOS output, or differential output.

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... lost you at the next part

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There's a couple of ways to implement the SPI version; you can have each CPLD have two SPI interfaces, a master and a slave (with each interface having sel/sck/mosi/miso), or you can do something like your diagram.

In either case, each board should have some sort of unique address.

Why? Well, there are two ways to use your board.

1) A big long shift-register.

In this case, whenever SEL asserts, bits shift into the shift register, until SEL deasserts. Pretty simple to understand.

2) Each CPLD is an individually addressable entity

Lets say you plan on cascading at most 16 boards. If you include a 4-bit DIP switch on the board, that DIP switch can be used to define a unique board ID that the CPLD can read.

The SPI interface can then be defined to have a protocol that includes an address phase, a read/write indicator, and a data phase.

The address phase of the transaction can contain the CPLD ID in the MSBs, and then the internal CPLD address in the LSBs. Eg., a 16-bit address would have the 4-bit ID followed by a 12-bit internal address.

Each CPLD has an FSM that starts when SEL asserts, and then once the CPLD ID is shifted in, checks it, and then either determines it is selected, or not.

The advantage of the latter scheme is that you can define your chain of CPLDs as an address map at the granularity of say 1-byte, so your read/write access time is much faster.

There's no need to start with (2), but its always easier to plan for the future by including a DIP switch or footprints for resistor pull-downs (the pull-ups on the I/Os can be used to create a high by default).

Cheers,

Dave

I quite like the RS485 solution but I wonder if it's overkill. All the daughtercards will be located quite close. Still, I'd rather play it safe.

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Connect SEL/SCK/MOSI signals to RS485/422 drivers and MISO to a receiver, and route the signals along with GND to a header.

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I followed you till this point but lost you at the next part

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Again, you'll need two of these interfaces; one as an SPI master, and one as an SPI slave. The first board in the daisy chain could be controlled from JTAG, and the remainder can daisy chain via SPI.

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In your explanation, does MOSI come from the previous CPLD in the cascade or from the uC? If it comes straight from the uC, how does the contents of the first CPLD in the cascade "spill over" onto to the next one?

I envisioned this as follows, but perhaps my solution is naive. Connect SEL, SCK, MOSI and MISO to the first CPLD. For the 2nd CPLD in the cascade, connect SEL, SCK (from the uC) but route Serial Out from the first shift register to it. This will be it's input. It should also have a Serial Out, which is connected to the first CPLD's Serial In. This allow the CPLDs contents to be read back in. All of these will be sent via RS485 which gives us greater noise immunity due to differential signaling. I'm quite bad with words, so here's a block diagram explaining what I meant (I omit the Rs485 in this)

http://i.imgur.com/5ym70.png

The above will only work for a Serial In Parallel Out shift register and not for a Parallel In Serial out shift register because the data cannot be read out from the last CPLD (and I need both).

What I don't understand in your solution is that, if MOSI comes from the uC, how do the bits from the first CPLD spill over onto the next CPLD in the cascade?

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A uC communicates with my CPLDs using SPI. What I'm not sure about is how to best cascade these CPLDs in order to obtain a larger shift register.

... I'd like to place these additional CPLDs on a different PCB. This has the advantage that I can simply extend the device when I need ...

I think buffering the signals would be good practice. But what would be the best way to actually connect the PCBs together?

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There are two solutions;

1. Using JTAG to control all the boards.

You want a single JTAG cable to control multiple boards, so you need a standard JTAG header on each board (the JTAG input connector), and then a buffer that drives TCK/TMS to the next board - that'll be a second JTAG header. The TDO bit on the CPLD will drive the TDI bit on the second JTAG header, and then you will want a jumper that selects the source for the TDO bit that drives the first JTAG header, either TDO from the second header if the board is in the middle of the daisy chain, or the TDO from the CPLD on that board, if it is the last in the chain.

2. SPI daisy chain.

What if your environment is really noisy, and the JTAG scheme does not work? Be conservative.

Connect SEL/SCK/MOSI signals to RS485/422 drivers and MISO to a receiver, and route the signals along with GND to a header. Again, you'll need two of these interfaces; one as an SPI master, and one as an SPI slave. The first board in the daisy chain could be controlled from JTAG, and the remainder can daisy chain via SPI.

Since the RS485/422 drivers are operated in a fixed direction, you do not need to worry about bus turnaround, so you can leave them enabled.

You could also use LVDS drivers/receivers for this application.

This will be a robust solution for noisy environments.

Cheers,

Dave