--- Quote Start ---
I quite like the RS485 solution but I wonder if it's overkill. All the daughtercards will be located quite close. Still, I'd rather play it safe.
--- Quote End ---
Its easy to put an RS485/422 driver/receiver footprint on a board, and assign differential pins to the header, but then also have a resistor that jumps the single-ended CPLD output onto the positive signal of the differential, you can also have a pull-down to gnd on the negative side of the differential too. That way you can load the board as LVCMOS output, or differential output.
--- Quote Start ---
... lost you at the next part
--- Quote End ---
There's a couple of ways to implement the SPI version; you can have each CPLD have two SPI interfaces, a master and a slave (with each interface having sel/sck/mosi/miso), or you can do something like your diagram.
In either case, each board should have some sort of unique address.
Why? Well, there are two ways to use your board.
1) A big long shift-register.
In this case, whenever SEL asserts, bits shift into the shift register, until SEL deasserts. Pretty simple to understand.
2) Each CPLD is an individually addressable entity
Lets say you plan on cascading at most 16 boards. If you include a 4-bit DIP switch on the board, that DIP switch can be used to define a unique board ID that the CPLD can read.
The SPI interface can then be defined to have a protocol that includes an address phase, a read/write indicator, and a data phase.
The address phase of the transaction can contain the CPLD ID in the MSBs, and then the internal CPLD address in the LSBs. Eg., a 16-bit address would have the 4-bit ID followed by a 12-bit internal address.
Each CPLD has an FSM that starts when SEL asserts, and then once the CPLD ID is shifted in, checks it, and then either determines it is selected, or not.
The advantage of the latter scheme is that you can define your chain of CPLDs as an address map at the granularity of say 1-byte, so your read/write access time is much faster.
There's no need to start with (2), but its always easier to plan for the future by including a DIP switch or footprints for resistor pull-downs (the pull-ups on the I/Os can be used to create a high by default).
Cheers,
Dave
Honored Contributor
