Honored Contributor
Honored ContributorI quite like the RS485 solution but I wonder if it's overkill. All the daughtercards will be located quite close. Still, I'd rather play it safe.
--- Quote Start --- Connect SEL/SCK/MOSI signals to RS485/422 drivers and MISO to a receiver, and route the signals along with GND to a header. --- Quote End --- I followed you till this point but lost you at the next part --- Quote Start --- Again, you'll need two of these interfaces; one as an SPI master, and one as an SPI slave. The first board in the daisy chain could be controlled from JTAG, and the remainder can daisy chain via SPI. --- Quote End --- In your explanation, does MOSI come from the previous CPLD in the cascade or from the uC? If it comes straight from the uC, how does the contents of the first CPLD in the cascade "spill over" onto to the next one? I envisioned this as follows, but perhaps my solution is naive. Connect SEL, SCK, MOSI and MISO to the first CPLD. For the 2nd CPLD in the cascade, connect SEL, SCK (from the uC) but route Serial Out from the first shift register to it. This will be it's input. It should also have a Serial Out, which is connected to the first CPLD's Serial In. This allow the CPLDs contents to be read back in. All of these will be sent via RS485 which gives us greater noise immunity due to differential signaling. I'm quite bad with words, so here's a block diagram explaining what I meant (I omit the Rs485 in this) http://i.imgur.com/5ym70.png The above will only work for a Serial In Parallel Out shift register and not for a Parallel In Serial out shift register because the data cannot be read out from the last CPLD (and I need both). What I don't understand in your solution is that, if MOSI comes from the uC, how do the bits from the first CPLD spill over onto the next CPLD in the cascade?
