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Altera_Forum's avatar
Altera_Forum
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12 years ago

Can't match timing for 80MSPS ADC with Cyclone/Arria/Stratix!?

Hi,

I've spent days on this and can't seem to meet timing. Coming here because I think I'm doing something wrong.

Tested development kits

Cyclone V GT. Prefer to work with this one. http://www.altera.co.uk/products/devkits/altera/kit-cyclone-v-gt.html

Arria V GX http://www.altera.co.uk/products/devkits/altera/kit-arria-v-starter.html

Stratix IV http://www.altera.co.uk/products/devkits/altera/kit-siv-gx.html

ADC = AFE5807 www.ti.com/litv/pdf/slos703c (http://www.ti.com/litv/pdf/slos703c)

12 bit. 80MSPS. 8 Channel.

LVDS data stream. DDR bitclock at 480MHz. Frame clock at 80Mhz.

Can't use alt_lvds because it supports only 10 bit deserializer. I want 12.

I use DDIO megafunction. Clock it using the bitclk. But I fail to meet timing no matter what I do.

Timing constraint file is given here. http://pastebin.com/5kmiffd0

So far, I have tried

PLL for bit clk. Source synchronous. Nope.

bitclk on multiple inputs. One for each channel. Thinking I can put a clock buffer outside. Nope.

bitclk via GCLK/RCLK. Nope

bitclk via dedicated/non-dedicated clock input pins. Nope

Sometimes, I barely meet setup but never hold times.

Is 480MHz input too high a bitclk for these FPGAs? Or am I making a mistake somewhere.

Is it possible for me to get it to work for the next bitclk edge?

e.g. I am ok with loosing the first bit of the first sample from the ADC. Then the bitclock aligns correctly.

Shouldn't matter in a long datastream.

Any help would be greatly appreciated.

Thanks

ZubairLK

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Update: Source Sync PLL for Stratix IV Dev Kit works. But that is v.expensive. I'd really like to get it to work with the Cyclone V GT kit..

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I see that this question remains unanswered by the gurus

    The data-sheet specifies a maximum bit-rate of 840 MBps for outputs, I expect the inputs not to run any faster, to the contrary :)

    So for Cyclone V (or IV or III) you need to lower the ADC's clock to 60 MHz or so , perhaps 70 MHz may also pass.

    I perused your .sdc file and that seems fine to me.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Besides Stratix, also Arria FPGA family can handle the required bit rate of 960 MBPS. Cyclone can't.

    There are different ways to receive 12 bit words with 10 bit limited SERDES blocks, receiving two 6 Bit half-words would allow to use still the advanced hardware features like DPA.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks for the input.

    For DDIO input, the limitation was more on the clock speed. I guess we can't push the device beyond the limits of the ip cores (LVDS 840Mbps for cyclone).

    I'll look into the alt_lvds for 6 bit half words.

    But I tried constraining the design for just 1 ADC channel using the bit clock.

    But it wouldn't constrain it.

    Does the LVDS megafunction use some dedicated high speed well-timed clock?

    Thanks

    Zubair