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Altera_Forum's avatar
Altera_Forum
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12 years ago

Can't match timing for 80MSPS ADC with Cyclone/Arria/Stratix!?

Hi, I've spent days on this and can't seem to meet timing. Coming here because I think I'm doing something wrong. Tested development kits Cyclone V GT. Prefer to work with this one. http...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Besides Stratix, also Arria FPGA family can handle the required bit rate of 960 MBPS. Cyclone can't.

There are different ways to receive 12 bit words with 10 bit limited SERDES blocks, receiving two 6 Bit half-words would allow to use still the advanced hardware features like DPA.