Can't match timing for 80MSPS ADC with Cyclone/Arria/Stratix!?

I see that this question remains unanswered by the gurus

The data-sheet specifies a maximum bit-rate of 840 MBps for outputs, I expect the inputs not to run any faster, to the contrary :)

So for Cyclone V (or IV or III) you need to lower the ADC's clock to 60 MHz or so , perhaps 70 MHz may also pass.

I perused your .sdc file and that seems fine to me.