Can't match timing for 80MSPS ADC with Cyclone/Arria/Stratix!?

Thanks for the input.

For DDIO input, the limitation was more on the clock speed. I guess we can't push the device beyond the limits of the ip cores (LVDS 840Mbps for cyclone).

I'll look into the alt_lvds for 6 bit half words.

But I tried constraining the design for just 1 ADC channel using the bit clock.

But it wouldn't constrain it.

Does the LVDS megafunction use some dedicated high speed well-timed clock?

Thanks

Zubair