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Altera_Forum
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16 years ago

Can't fit fan-out of node into a single clock region

Hi, I've encounterred with this promblem.I use the ep2c20f256c8 ,design with 1 pll and 20 channels of lvds transmitter. input clock freq is 50MHz,pll output clocks' f is 200MHz,100MHz,50MHz,and it...
Altera_Forum's avatar
Altera_Forum
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16 years ago

That sounds like a PLL setting error. When you were in the MegaWizard, and setting up the PLL, did you have Cyclone II selected as the device family? The PLL capabilities are different from family to family, so it may just be that for whatever reason, the combination of those clocks don't work with the Cyclone II pll. (I haven't tried). The error message is a bit confusing. I haven't seen that particular message.

However can easily try to use the first PLL setting and just supply a simple flop to divide it externally from the PLL.

Pete