Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Can I configure the multi-device like this?

In My project, There are two CycloneIII device, the one is EP3C10 and the other is EP3C25. But they receive different .sof data. Can i configure them successful followed the Figure9-4 or Figure9-5 in Handbook of CycloneIII?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Yes you can use the scheme in figure 9-4 and place the two images in the EPCS flash. Just ensure that the EPCS is big enough to hold both images.

    You can't use the scheme in figure 9-6 though as your FPGAs are different, and can't use the same image file.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Yes you can use the scheme in figure 9-4 and place the two images in the EPCS flash. Just ensure that the EPCS is big enough to hold both images.

    You can't use the scheme in figure 9-6 though as your FPGAs are different, and can't use the same image file.

    --- Quote End ---

    Thank Daixiwen at first. As you guide. We can convert two sof data into one pof configure file for EPCS. So I think figure9-4 and figure9-5 is the same case that multi sof file configured for multi device and each one receive the same pof that packaged by several sof data but they only use one part belong to itself. Figure9-6 is suitable for the application that all of devices receive the same and only single sof data. they must be the same devices for figure9-6 application. This is all my understanding. Hope to get your further check. Thanks again.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Yes you understood in right. In figure 9-5 you have two .sof configurations in the flash, and the first one will be uploaded to the FPGA on the left, while the second one will be uploaded to all the FPGAs on the right.