Can CPU win arbitration during DMA operation to the same data bus?

Edit: I misread you, as if you were DMAing from the flash to the SSRAM.

The Qsys fabric Master1 access Slave1 while Master2 accesses Slave2 without contention.

What I wrote below only applies when two or more masters try to access the same slave.

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The CPU will given access.

The arbitration scheme uses a fairness scheme. By default, it gives each master one access, round robin. If needed, you can change the weights in Qsys.

Check Qsys interconnect handbook, 7-10.