Honored ContributorI'm looking at making a CameraLink transmitter using the GX transmitter blocks in the Cyclone IV. ALTGX won't allow me to select a channel width of 7 which is the serialization factor. Is this an inherent limitation?
Honored ContributorSee Figure 1-3 of the transceiver manual: https://www.altera.com/en_us/pdfs/literature/hb/cyclone-iv/cyiv-52001.pdf
The "Byte Serializer" is the "inherent limitation". CameraLink is very easy to implement just using ALTLVDS and LVDS I/O pins, with obvious limitations of the I/O pin capabilities.Honored ContributorThanks ted. Yes, using ALTLVDS would be simpler, it's the "obvious limitations of the I/O pin capabilities" I'm worried about. CameraLink at 85Mhz requires an I/O toggle rate of ~298Mhz. The Cyclone IV I7 device specifies a max toggle rate of 370Mhz for true LVDS, I guess this is OK. The output jitter is 500ps p-p max, which is about 30% of UI. This seems like a lot, maybe OK.
I also have to consider adding LVDS buffers to the FPGA to protect it from the "outside world". Given that, I might as well just use a CameraLink transmitter chip (DS90CR287) and save myself the FPGA coding. The GX outputs seemed like an elegant solution to all the above, plus I gets some extra features like programmable output level and pre-emphasis. These are the tradeoffs I'm struggling with at the moment.Honored ContributorThanks for posting this question. I am doing the same thing. This is post was very helpful to me. Joe
Honored ContributorGlad it was useful. I ended up using the DS90CR287.
Honored Contributorthanks for the sharing.
Honored ContributorHi, have a question that I hope someone can answer. I'm looking at the DS90CR287 device and also the document "Camera Link: Specifications of the Camera Link Interface Standard for Digital Cameras and Frame Grabbers". On page 2-1 they mention four enable signals: FVAL, LVAL, DVAL and Spare. However, I don't see these as inputs on the DS90CR287 device. How to I add these four signals?
Next, I have two video streams each stream has its own clock. I assume that I will need two DS90CR287 devices and according to page 5-2 it looks like I could use only one MDR-26 pin connector, but that does not agree with page 3-1. What am I missing here? Thanks, joeHonored ContributorSee table 4-1 for the mapping of FVAL, etc. to the DS90CR287 pins. Note also the strange mapping of data bits.
Two video streams with independent clocks will require two DS90CR287s. I see your confusion regarding pages 5-2 and 3-1. I'm not aware of any frame grabbers that will support two, independent CameraLink inputs with different clocks on the same MDR-26 connector. They may be out there though.Honored ContributorThank you so much. Now things make sense. One more question. My video image is 14-bits per pixel, so what do I do with the unused bits, tie to ground? Thanks, Joe
Honored ContributorCameraLink supports 14 bit monochrome in the Base configuration (Table C-1). Unused inputs on the DS90CR287 should be grounded.
Honored ContributorThat's even better. I'm looking at Table 5-1 for the Base Config. and please correct me if I'm wrong here. I would connect the DS90CR287 to Channel Link Signals X0+-, X1+-, X2+- and X3+-? Now what should I connect to SerTC+-, SerTFG+-? I'm connecting to a CCD detector and the fpga will drive the DS90CR287. I'm only getting image from the CCD and not communicating with it.
