Cache in NIOS II

Hello,

I need to implement a configurable direct mapped cache for the Nios-II and describe the hit rate for a parallel program as the number of processors is increased from 1 to 3.

I'm doing this for school. I've been told that I haveto do this using VHDL.

Is the cache already implemented or should I add a component in the SOPC builder?

I looked at this http://www.altera.com/literature/hb/nios2/n2sw_nii52007.pdf but I didn't find it useful (for VHDL at least).

Any advice would be appreciated.

Best regards,

Khalid