Buttons communication problem NIOS II

Thank you for ~button, I changed it. For the leds, I don't know I am gonna check this. I have a Cyclone III C25 from Altera.

When doing further tests, I noticed that button always remained at 0. Is there an initialisation to make to the variable button (knowing that I use the pooling method)? Why button value does not change ?

If you have the "Cyclone III FPGA Starter Board" (Neek), LEDs are anode common on it, so you dont' need one's complement. What do you get when doing printf("%d",button);?

do signaltap button signals change when a button is pressed?

SignalTap is 1111 when I don't press any button. When pressing a button, the signal goes down to 0 (for example, pressing button1 gives 0111).

When doing printf("%d",button), the console keeps displaying 0 whatever I do, pressing or not a button.

I checked I had the right names by looking at system.h.

How can I check the connection between PIO's export signals and buttons ? I am a newbie in quartus II.

It seems like buttons are just for reading. I put the module definition below. Am I right ? Any other idea ?

In the module, I chose "input ports only" and did not specify any input options.

Maybe it comes from my pin assignment, I only added the following assignments in my tcl :

set_location_assignment PIN_F1 -to button[0]

set_location_assignment PIN_F2 -to button[1]

set_location_assignment PIN_A10 -to button[2]

set_location_assignment PIN_B10 -to button[3]

I let the I/O standard to 2.5V and the current strength to 8mA. May it come from this ?

Thanks,

Myriam

Here is my module :

module button_pio (

// inputs:

address,

clk,

in_port,

reset_n,

// outputs:

readdata

)

;

output [ 3: 0] readdata;

input [ 1: 0] address;

input clk;

input [ 3: 0] in_port;

input reset_n;

wire clk_en;

wire [ 3: 0] data_in;

wire [ 3: 0] read_mux_out;

reg [ 3: 0] readdata;

assign clk_en = 1;

//s1, which is an e_avalon_slave

assign read_mux_out = {4 {(address == 0)}} & data_in;

always @(posedge clk or negedge reset_n)

begin

if (reset_n == 0)

readdata <= 0;

else if (clk_en)

readdata <= read_mux_out;

end

assign data_in = in_port;

endmodule

Thanks for helping me. Here is my top level entity :

module niossram (

// inputs:

osc_clk,

reset_n,

button,

// outputs:

flash_ssram_a,

flash_ssram_d,

led,

ssram_adsc_n,

ssram_bw_n,

ssram_bwe_n,

ssram_ce_n,

ssram_clk,

ssram_oe_n

);

input osc_clk;

input reset_n;

input [ 3: 0] button;

output [ 23: 0] flash_ssram_a;

inout [ 31: 0] flash_ssram_d;

output [ 3: 0] led;

output ssram_adsc_n;

output [ 3: 0] ssram_bw_n;

output ssram_bwe_n;

output ssram_ce_n;

output ssram_clk;

output ssram_oe_n;

wire [ 3: 0] led_n;

wire [ 3: 0] button_n;

assign ssram_clk = osc_clk;

assign led = ~led_n;

niossram_sopc niossram_sopc_instance

(

.in_port_to_the_button_pio (button_n),

.adsc_n_to_the_ssram (ssram_adsc_n),

.bw_n_to_the_ssram (ssram_bw_n),

.bwe_n_to_the_ssram (ssram_bwe_n),

.chipenable1_n_to_the_ssram (ssram_ce_n),

.address_to_the_ssram (flash_ssram_a),

.data_to_and_from_the_ssram (flash_ssram_d),

.clk (osc_clk),

.out_port_from_the_led_pio (led_n),

.outputenable_n_to_the_ssram (ssram_oe_n),

.reset_n (reset_n),

);

endmodule