Forum Discussion
Sayali
New Contributor
New ContributorBUS TAP in quartus prime lite
In custom designed PCB board with Intel MAX V CPLD, In order to feed 9 down to 0 counter output to one of the inputs of NOR GATE, i am not finding direct bus tap option available in Quartus prime 23....
FvM
Super Contributor
Super ContributorHi,
as far as I'm aware of, a bus tap is connecting a single bus bit. The drawing however suggests a logic operation, e.g. or_reduce(). Does Xilinx provide a feature to assign a logic operation to a bus tap?
Or reduce is available as operator in VHDL or Verilog, you can make a block schematic symbol performing this function, but why?
Explicitely connecting bus bits to or gate doesn't seem too complicated.
