Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Burst Reads with NIOS II

I am trying to use the NIOS processor to read some debug data that has been dumped on a Memory Mapped device on the Avalon bus, using burst reads. However, I am stuck in writing the C code. I am not able to find the routine that allows me to specify the burst count value etc. I have seen only the IORD routines, which appear to be for a single 32 bit read only.

How can one perform burst reads over the avalon bus for large amounts of data transfer and what are the C funtions to be used?

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Yeah, I found some reference designs using DMA. Just curious to know if the NIOS directly could issue burst reads. Thanks for your reply Appus.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The caches in the Nios CPU can issue burst reads. When you perform a regular read operation (i.e. through a pointer and not an IORD macro) and if you have a data cache, the cache will read a full cache line. If you enabled bursts access for the cache, it will do so with a burst read.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Daixiwen, can you give an example code snippet of how exactly i can issue reads to cache memory? Is there anything i need to do while configuring the NIOS core so as to enable cache? Right now I have used only the basic settings.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Yes, in SOPC builder, open the settings of the Nios core, go in the cache/memory access tab ( I don't remember the exact name) and enable the cache and the burst access.

    To read memory, just use standard C code. Create a pointer, make it point to the memory you want to read and do the read operation.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The read/write bursts from the instruction and data caches are independent of your code. The caches are present to perform more efficient accesses to the memory so it's not something you can control much in your own application. You can control whether or not to access cache-able memory but if you bypass the cache then the Nios II core *will not* perform burst transaction to/from the memory.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Refer to the 'initda' and 'flushda' instrctions.

    I think the former invalidates a specific cache line (so the cache won't write it out), and the latter forces the (dirty) cache line to be written.

    I can't see the instruction that would marke a cache line 'valid' without doing the associated read.

    (I've not actually used any of these instructions....)