Hi All, I am looking for information on how to concatenate a .elf and a .sof file into a single .rbf file. The elf file loads Nios data and instructions into an external SDRAM. Any information/suggestions would be most appreciated. thanks. V

Quartus already does RBF file output, You have to select an option to enable rbf generation. For ELF, You need to convert it to HEX using elf-to-hex and later You need a 3rd party tool to convert HEX to BIN. Remember, that RBF file is LSB 1st afaik, so You need to do a bit swap.

I'm aware that Quartus already does RBF file output. There are some finer points that i'm curious about. 1. If I build an SOF with the nios elf file included, can it be converted to an RBF that will initialize the nios memory? 2. If nios memory is in external SDRAM, will the RBF initialize SDRAM? 3. Has anyone done this? Best regards, V

--- Quote Start --- 1. If I build an SOF with the nios elf file included, can it be converted to an RBF that will initialize the nios memory? --- Quote End --- How do You do that? You mean You generate SOF file, which has on-chip memory initialization file inside? If yes, then Nios CPU has to have startup vectors to point to on-chip memory. --- Quote Start --- 2. If nios memory is in external SDRAM, will the RBF initialize SDRAM? --- Quote End --- NO. You need to add on-chip memory as I've mentioned in (1), then write a small bootloader, which would fit into the on-chip memory and get executed after system startup. That bootloader will have to copy all the required program data to SDRAM and jump to that place. --- Quote Start --- 3. Has anyone done this? --- Quote End --- Yes, I use on-chip memory of 8KB size with my 4.2KB bootloader pre-compiled. The bootloader copies all the Nios binary from serial flash to SDRAM and executes the main program.

--- Quote Start --- How do You do that? You mean You generate SOF file, which has on-chip memory initialization file inside? If yes, then Nios CPU has to have startup vectors to point to on-chip memory. NO. You need to add on-chip memory as I've mentioned in (1), then write a small bootloader, which would fit into the on-chip memory and get executed after system startup. That bootloader will have to copy all the required program data to SDRAM and jump to that place. Yes, I use on-chip memory of 8KB size with my 4.2KB bootloader pre-compiled. The bootloader copies all the Nios binary from serial flash to SDRAM and executes the main program. --- Quote End --- I have a Nios program too big to fit into on-chip memory (similar to simple socket server). I have external SDRAM and flash with active parallel setup (no EPCS). Do I also need a bootloader?

Yes, You need a bootloader, which would fit into on-chip memory. This bootloader will have to copy Nios program from flash to SDRAM and start it.

Building RBF with SOF and ELF, External SDRAM

19 Replies

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
What's the point of that slow clock in the system? Nios II/f will definitely run on 75MHz, so I'd just use the same clock in all components. Are You using JTAG_UART in bootloader app? E.g. doing a printf() or something?
--- Quote End ---

I changed all the clocks to 75 except the input of the PLL, did not seem to make a difference. There are no prints in my .hex code, literally just the sys_init, 2 usleeps, and 2 IOWR to the LED to blink the LED. Also in the BSP editor, I have the stderr, input, output set to none instead of JTAG_UART.

I did notice something interesting. Kind of confusing, if I...

Shut off power, turn on power
Wait for the config to finish, the LED doesn't blink (program isn't running)
Then program the FPGA in Quartus, the LED doesn't blink (program isn't running)
Then run the Nios download from Eclipse, the LED starts to blink (program is running)
Then reprogram the FPGA in Quartus, the LED stops while it's being programmed, then starts blinking again (program is running again)

I don't know what to make of that. Why would it not work after being programmed from a power reset, but still work from nios2-download, even after reprogramming the FPGA again? Maybe that will help pinpoint the problem.
Altera_Forum
Honored Contributor
13 years ago
Paste the source code to pastebin.org

It should work if the hex is correct.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Paste the source code to pastebin.org

It should work if the hex is correct.
--- Quote End ---

Blocked, but I attached the file.
flash_leds(2).txt4 KB
Altera_Forum
Honored Contributor
13 years ago
I came up with the most basic SOPC system and Nios design I could (basically just CPU, on chip RAM, LEDs, and sysid) and it works on powerup. I don't know if this is more discouraging or encouraging.

Altera_Forum

Honored Contributor

13 years ago

You don't need that init stuff... Where did You find that? Try this:

# include "altera_avalon_pio_regs.h"# include "system.h"# include <stddef.h>
int main(void) {
while (1)
  {
    usleep(1000*1000);
    IOWR_ALTERA_AVALON_PIO_DATA(USER_LEDS_BASE, 1);
    usleep(1000*1000);
    IOWR_ALTERA_AVALON_PIO_DATA(USER_LEDS_BASE, 0);
  }
  return 0;
}

Altera_Forum
Honored Contributor
13 years ago
The init stuff was in the advanced boot loader. I did this:

Took out the init stuff
Set the system timer to none in the BSP
Changed the device configuration to active serial in the device and pin options (this is wrong, mine is active parallel)

And now the LED is flashing on power up :D No idea which one of these things made a difference.

I'm going to run with this, hopefully I can handle it from here! Thanks so much for your help.

By the way I figured out the other clock was because timing fails without it. Whoever worked on this before must have discovered that.
Altera_Forum
Honored Contributor
13 years ago
Too much changes to make a good conclusion, but I believe timer has nothing to do with the startup. It was probably that init stuff...
Altera_Forum
Honored Contributor
13 years ago
My need is similar to yours Kirshna, The reason I'm using SDRAM is because the program is too big for on-chip RAM. Using nios2-download, I end up with the elf image running in SDRAM. So, what is the "magic" that allows this to work? If that can be duplicated in a stand-alone situation, then the problem is solved.

the fundamental question is what is Altera's recommendation for users who need to have the CPU on the board with the FPGA load the FPGA pattern and the nios elf image from files accessible to the CPU. Is it really such a big issue that the nios runs from SDRAM? This means that the FPGA load image can be upgraded in the field. This seems like a common need. We are not trying to do something out of the ordinary. What is the "offical" Altera solution?
Altera_Forum
Honored Contributor
13 years ago
Well You can use only pointers to copy all the data instead of memcpy() and it should save some space. Also I'd offer to use CRC for the binary data, since it is pretty common to have an invalid bit or byte in like 100 boot-ups.

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Building RBF with SOF and ELF, External SDRAM

19 Replies

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