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What's the point of that slow clock in the system? Nios II/f will definitely run on 75MHz, so I'd just use the same clock in all components. Are You using JTAG_UART in bootloader app? E.g. doing a printf() or something?
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I changed all the clocks to 75 except the input of the PLL, did not seem to make a difference. There are no prints in my .hex code, literally just the sys_init, 2 usleeps, and 2 IOWR to the LED to blink the LED. Also in the BSP editor, I have the stderr, input, output set to none instead of JTAG_UART.
I did notice something interesting. Kind of confusing, if I...
- Shut off power, turn on power
- Wait for the config to finish, the LED doesn't blink (program isn't running)
- Then program the FPGA in Quartus, the LED doesn't blink (program isn't running)
- Then run the Nios download from Eclipse, the LED starts to blink (program is running)
- Then reprogram the FPGA in Quartus, the LED stops while it's being programmed, then starts blinking again (program is running again)
I don't know what to make of that. Why would it not work after being programmed from a power reset, but still work from nios2-download, even after reprogramming the FPGA again? Maybe that will help pinpoint the problem.
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