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Honored Contributor
Honored Contributorbuffer for clock signal?
Do Quartus has an buffer for split the clock signal (200MHz)? ----------------------------- clock (200MHz) | | | | | | |...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- because the quartus do: what is "ripple clock"? Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "inst5" as buffer Info: Detected ripple clock "myflipflop:inst14|Q" as buffer Info: Detected gated clock "inst18" as buffer --- Quote End --- Hi, I think the Info is a little bit misleading. It only means that Quartus found 3 nodes which drives the clock inputs of e.g. registers. You don't need to do any buffering here, but this kind of clock generation could cause a lot of timing violations. Kind regards GPK
