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Honored Contributor
Honored Contributorbuffer for clock signal?
Do Quartus has an buffer for split the clock signal (200MHz)? ----------------------------- clock (200MHz) | | | | | | |...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi! no, the 200 MHz clock is the out of pll, it is internally of fpga. ------200MHz------ AND PORT------------ . ..............................................| | . ..............................................| | . ..............................................| | . ............................................nodes --- Quote End --- Hi, why do you want to place a buffer at that point ? Kind regards GPK
