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Thank you Mr KAZ.
I hope you check that file and see if it can help to model our loop. (Actually it does have different behavior when you change - to + in error signal).
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I did some read on that file. This guy is probably funny trying to match some absolute phase of two signals. This is meaningless unless he got some specific application.
absolute phase is meaningless to control as signal could arrive at any phase and this is immaterial in most radios (possibly all radios). what we want is to control frequency through phase until rf signal is centred on dc. Phase then doesn't matter and you should not compare phase if signals are of different frequencies. don't mix up with PLL that generate clock in phase with ref.
Honored Contributor
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