bitstream to netlist

Yes. Put it in the part and see if it works. (I'm joking).

By netlist, do you mean the RTL? If so, the answer is no. There is no way to turn this into something understandable. (Altera probably understands it, but for equivalency you generally want a third party tool. Having Altera check its own synthesis algorithms is generally counter-productive, as it's far too easy to make the same mistake twice).

There are Formal Verification tools. They would check the post-fit netlist(basically the timing simulation model) against the original RTL. There was a big push for these as ASIC designers started using FPGAs, as it makes complete sense with an ASIC, since you can't try the device in system before tape-out, and it's so expensive to fix a mistake(both in $ and time). But when asked why they needed to do it for FPGA design, they generally just said, "Because that's what we do for ASICs".

From what I've heard, formal verification is not easy, and I would generally recommend against it unless it was an absolute requirement or there was a really good reason. I was joking a bit, but being able to run the FPGA in-system tends to be a much better test than formal verification or huge timing simulations. (I'm sure there are varying opinions on this...)