Bidirectional, tri-state buffer, VHDL problem

I m working with tg68k mc68k core emulation for FPGA. When i compile code i get 31 ADRESS BUSS pins, also 16 input, and 16 output pins. I need to join those 16 in and out pins to get 16 bidirectional pins for DATA BUS. I write some VHDL but i have some problems. Code generates 16 bidirectional pins as i wanted but also there are 16 input and 16 output pins, and no ADDRESS BUSS pins. As i can see my code have influence on all pins, and i just want to have influence on 16 in and 16 out pins to join them in 16 bidirectional pins using tri-state buffer.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY data_bus IS
PORT(
data_bus : inout STD_LOGIC_VECTOR (15 downto 0);
oe : IN STD_LOGIC;
input : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END data_bus;
ARCHITECTURE signals OF data_bus IS
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);
signal data_oe : STD_LOGIC;
BEGIN
PROCESS(oe)
BEGIN
IF oe = '1' THEN 
data_bus <= data_out;
ELSE
data_bus <= "ZZZZZZZZZZZZZZZZ";
data_in <= data_bus;
END IF;
END PROCESS;
END signals;