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Honored Contributor
Honored ContributorBidirectional, tri-state buffer, VHDL problem
I m working with tg68k mc68k core emulation for FPGA. When i compile code i get 31 ADRESS BUSS pins, also 16 input, and 16 output pins. I need to join those 16 in and out pins to get 16 bidirectional...
Altera_ForumHonored Contributor
Honored ContributorGive this a try:
Remove the whole process, and replace it with the following:data_in <= data_bus;
data_bus <= data_out when oe='1' else (others => 'Z');
