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Altera_Forum
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15 years ago

Bidirectional, tri-state buffer, VHDL problem

I m working with tg68k mc68k core emulation for FPGA. When i compile code i get 31 ADRESS BUSS pins, also 16 input, and 16 output pins. I need to join those 16 in and out pins to get 16 bidirectional...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Give this a try:

Remove the whole process, and replace it with the following: 

data_in <= data_bus;
data_bus <= data_out when oe='1' else (others => 'Z');

This the way I usually describe tristateable signals.

Good luck!

Ben