Beginner questions on HDL component mapping

Your example doesn't fit your question. CLK isn't a port in the entity, it's a signal.

If the CLK ports would be outputs at both components, you get a "multiple driver" error. The signal CLK can have only one driver. Please consider that VHDL is a hardware description language. The design must be implementable in hardware. Try to draw a hardware logic circuit representing your VHDL design. Where is each signal originated from and where goes it to?

P.S.: Without knowing the component declarations, it's unclear what the above example means.