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Altera_Forum's avatar
Altera_Forum
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18 years ago

Beginner question: FPGA timings

I'm very new to the FPGA world, so my question is probably naive.

So, I chose a very standard Cyclone II EP2C20F484C7N device.

I created a very simple design, and found that the latency from input pin to output pin can't be lower than 8.6ns. As I'm reading the Cyclone II device handbook, Chapter 5, Timing specifications, I find a nice explanation for my timings: there is a delay of about 4ns from pin to cell, and again from cell to pin, added to the smaller internal delays for each gate. So far so good.

Now, it looks like I can't get any output in less than 10ns with this chip. And I can't even make it works on something in less than 4ns. So why is its maximum clock rate at around 500MHz ? How are these numbers related ? How are they both related the the sentence "The fastest FPGA broadly available run at around 600MHz" ?

I apologize once again for this beginner question. Thanks in advance for any answer.

Jerome.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    The delay you described sounds like a pin-to-pin tpd delay (no register involved). The frequency you saw in the documentation was probably for internal paths from a register to a register. FPGAs typically can have much faster internal paths than I/O paths.

    For an ordinary I/O setup with system synchronous timing, you would have a register in one device driving a register in another device with a common clock for the two devices. The I/O frequency is limited by the tco of the driving device plus the effect of the board delays on the data and clock plus the tsu of the receiving device.

    I/O paths can be very fast too with a technique like a source synchronous interface. In that case, the I/O timing might be limited by the maximum toggle frequency of the I/O standard (documented in the device handbook). It won't be limited by tco+tsu of the two devices.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Brad's summary is great. if you don't need a single clock cycle Tpd, you get the fastest performance clock frequency using flip flops in the I/O element. If you do need the fastest Tpd from input pin to output pin, sometimes the tools do not do a great job without a little help. If you haven't already, constrain the input and output pins next to eachother. It sounds like you are already asking for a fast as possible time with timing constraints.