Beginner question: FPGA timings

The delay you described sounds like a pin-to-pin tpd delay (no register involved). The frequency you saw in the documentation was probably for internal paths from a register to a register. FPGAs typically can have much faster internal paths than I/O paths.

For an ordinary I/O setup with system synchronous timing, you would have a register in one device driving a register in another device with a common clock for the two devices. The I/O frequency is limited by the tco of the driving device plus the effect of the board delays on the data and clock plus the tsu of the receiving device.

I/O paths can be very fast too with a technique like a source synchronous interface. In that case, the I/O timing might be limited by the maximum toggle frequency of the I/O standard (documented in the device handbook). It won't be limited by tco+tsu of the two devices.