Beginner question: FPGA timings

Brad's summary is great. if you don't need a single clock cycle Tpd, you get the fastest performance clock frequency using flip flops in the I/O element. If you do need the fastest Tpd from input pin to output pin, sometimes the tools do not do a great job without a little help. If you haven't already, constrain the input and output pins next to eachother. It sounds like you are already asking for a fast as possible time with timing constraints.