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Altera_Forum
Honored Contributor
Honored ContributorBCD counter vhdl code
I am a newbie quartus user.. please help me thanks
http://i54.tinypic.com/2zp2p3p.png This is my written code: library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all; entity d4 is
port (reset, sensor, load :in std_logic;
p :in std_logic_vector (5 downto 0);
led_on :out std_logic;
q :out std_logic_vector (5 downto 0));
end d4; architecture flow of d4 is signal count_sig : unsigned (5 downto 0);
signal load_sig : unsigned (5 downto 0); begin
process (sensor, reset, load, p)
begin
if (reset = '1') then
count_sig <= "000000"; elsif rising_edge (sensor) then
if (count_sig = 32) then
count_sig <= "000000"; else
count_sig <= count_sig + 1; if (load = '0') then
count_sig <= load_sig; else
count_sig <= count_sig + 1;
end if;
end if;
end if;
end process;
q <= std_logic_vector (count_sig); end flow;
------------------------------------------------------------------------ I did not add LED_ON in the code because i don't know the correct way to to put in the LED, always getting error when i try to put in LED code.. and i can't make P to activate Q when load is low. i don't know what i am talking about too. Please help me ! appreciate if u do so :confused:
16 Replies
Altera_Forum--- Quote Start --- Truely. You need a type cast when assigning std_logic_vector to unsigned. Why don't you simply correct it and proceed. --- Quote End --- how do u do that lol .. sry i am really a noob my lecturer didn't taught us trial and error..- Altera_Forum--- Quote Start --- Error (10476): VHDL error at d4.vhdl(27): type of identifier "p" does not agree with its usage as UNSIGNED type --- Quote End --- Truely. You need a type cast when assigning std_logic_vector to unsigned. Why don't you simply correct it and proceed.
- Altera_Forum--- Quote Start ---
Try this. --- Quote End --- Error (10476): VHDL error at d4.vhdl(27): type of identifier "p" does not agree with its usage as UNSIGNED type thanks for assisting, it's not only the LED that i don't know about .. i feel that my code is not written properly and i can't find out the reason because i was not taught properly.. this one is way beyond my levellibrary ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity d4 is port (reset, sensor, load :in std_logic; p :in std_logic_vector (5 downto 0); led_on :out std_logic; q :out std_logic_vector (5 downto 0)); end d4; architecture flow of d4 is signal count_sig : unsigned (5 downto 0); signal load_sig : unsigned (5 downto 0); begin process (sensor, reset, load, p) begin if (reset = '1') then count_sig <= "000000"; elsif rising_edge (sensor) then if (count_sig = 32) then LED_ON <= '1'; count_sig <= "000000"; else LED_ON <= '0'; count_sig <= count_sig + 1; if (load = '0') then count_sig <= p; end if; end if; end if; end process; q <= std_logic_vector (count_sig); end flow; - Altera_Forum
Try this.library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity d4 is port (reset, sensor, load :in std_logic; p :in std_logic_vector (5 downto 0); led_on :out std_logic; q :out std_logic_vector (5 downto 0)); end d4; architecture flow of d4 is signal count_sig : unsigned (5 downto 0); signal load_sig : unsigned (5 downto 0); begin process (sensor, reset, load, p) begin if (reset = '1') then count_sig <= "000000"; elsif rising_edge (sensor) then if (count_sig = 32) then LED_ON <= '1'; count_sig <= "000000"; else LED_ON <= '0'; count_sig <= count_sig + 1; if (load = '0') then count_sig <= p; end if; end if; end if; end process; q <= std_logic_vector (count_sig); end flow; - Altera_Forum
is LED_ON a predefined output?
It's the second time i read about it. - Altera_Forum
LED_ON is just an output, you can assign it anywhere you want:
LED_on <= '1'; or LED_on <= some_other_signal; or if something_happened then led_on <= '1'; else led_on <= '0'; end if; etc.
