BCD counter vhdl code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity d4 is
port (reset, sensor, load :in std_logic;
p :in std_logic_vector (5 downto 0);
led_on :out std_logic;
q :out std_logic_vector (5 downto 0));
end d4;
architecture flow of d4 is
signal count_sig : unsigned (5 downto 0);
signal load_sig : unsigned (5 downto 0);
begin
process (sensor, reset, load, p)
begin
if (reset = '1') then
count_sig <= "000000";
elsif rising_edge (sensor) then
if (count_sig = 32) then
LED_ON <= '1';
count_sig <= "000000";
else
LED_ON <= '0';
count_sig <= count_sig + 1;
if (load = '0') then
count_sig <= p;
end if;
end if;
end if;
end process;
q <= std_logic_vector (count_sig);
end flow;