AXI read channel - signal rlast "missing"

Hi BadOmen,

Thanks for your answer! However, I doubt, that my problem is to be solved by advising Quartus to prevent some of my logic being optimized away.

I mean, the rlast signal is defined in the ARM AXI documentation and therefore, if QSys is AXI compatible, the according master in my system (the LWHPS2FPGA bridge) shoulkd implement that signal, too. QSys should be able to connect my AXI compatible slave to the AXI compatible master correctly and therefore should take care that specification signals should not be "optimized" away.

So I think, that there could be three reasons for my problem:

First, I misunderstand the AXI protocol and therefore did not handle the master read in my component correctly. This would include that the rlast signal isn't required at all and I'm focusing on the wrong thing here. This could be because I do not find ANY rlast signal in my whole system. As I said, the LED Avalon memory slave component works fine via the LWHPS2FPGA bridge. I know that the QSys interconnect connects the Avalon slave to the AXI master in the bridge and maps all required signals properly in order to obay their specifications. Now, if I do not find any rlast signal in my design, then why is the interconnection between avalon and AXI working in the LED slave? In my opinion there, too, must be a rlast signal at a certain conversion level.

Second, I do not handle the signals arlen, arburst, arsize correctly in my component and therefore, the read on my component fails. I know, that I do not handle those signals at all in my component. That is because I do not think, that (with the given data on that signals that can be seen in the Signal Tap shot) I do not have to handle anything because it is a single 32bit read by the master on my component so that I just put one 32 bit value on the read data bus and set all handshake lines correctly. But maybe sombody does find that this is not eneough. I would be happy about any advise.

Third, there is an error in the QSys interconnect generator that it just does not care about the rlast signal. I do not believe that this is the case but it should be on my list, I think.

I would be happy if I could find any working example of an AXI component in VHDL that I can connect to the LWHPS2FPGA or HPS2FPGA Masters of the Cyclone V. But until now, I was not able to find one. I just do find avalon custom component examples where the QSys interconnect takes care of protocol conversion.

I really want to use AXI in my upcoming project because I would like to use similtanious writes and reads without any data buffering or additional stuff between the AXI master and slave.

Regards,

Maik