AXI read channel - signal rlast "missing"

If you want to prevent nets from being optimized away you can try this (I copied this from the VHDL templates in Quartus II):

-- Prevents Quartus II from minimizing or removing a particular

-- signal net during combinational logic optimization. Apply

-- the attribute to a net or variable declaration.

attribute keep : boolean;

attribute keep of <object> : <object_class> is true;

Unfortunately I don't remember VHDL well enough to know how that code is supposed to behave. The lack of a defined reset condition is throwing me off.