--- Quote Start ---
In the documention they say you can choice either for AXI or Avalon-MM. I tend to go for the AXI bus because this way i don't have to translate the Avalon-MM to AXI interface and the complition signal is also usefull.
--- Quote End ---
Qsys will insert adapter logic, so the need for conversion is less of a concern.
Personally I would base the decision on which interface is well-supported by Altera's verification suite. Up until recently, only the Avalon-MM interfaces had decent verification support, i.e., BFMs. Altera does have support for AXI, but its via Mentor Graphics BFMs. I have not tested the AXI BFMs.
--- Quote Start ---
And connected to this question. I want to connect my own FPGA blocks with Port map ( A => B ), Not using Qsys, (because Qsys automatically uses Avalon) to the AXI interface. would this be even possible ?
--- Quote End ---
Yes, its trivial. I have a number of designs with a single Avalon-MM master (based on an FTDI USB-to-FIFO bridge) and one or a few slaves (RAM + registers) and for testing I just connect those directly together.
However, its also easy to connect them with Qsys. The generated code is easy to read, so you can open up the top-level file and check that the Qsys system matches what you expect.
Cheers,
Dave
Honored Contributor
